A typical analog video signal 11 for driving an analog video display is illustrated in FIG. 1. As shown in FIG. 1, the analog video signal 11 is a composite signal having lines of analog data 12 combined with other sweep and synchronization (sync) signals, which include blank levels referred to as a front porch 14a and a back porch 14b, and include a sync level 16. A blank period 14' is defined as a time period when the analog video signal 11 exhibits the front porch 14a, the sync level 16, and the back porch 14b, and a sync period 16' is defined as the time period in which the analog video signal 11 exhibits the sync level 16. The front porch 14a essentially cues the electron beam associated with a raster display to turn off when the beam sweeps from the end of a scan line to the beginning of the next scan line. The sync level 16 cues the electron beam to change either a scan line or a frame, depending upon its time period, and/or to reset counters and other support circuitry. When the sync level 16 cues a scan line, then it is referred to as a "horizontal sync" (Hsync). When the sync level 16 cues a frame, i.e., when it exhibits an extended time period, then it is referred to as a "vertical sync" (Vsync). Furthermore, the back porch 14b permits initialization of the electron beam and other support circuitry prior to acting upon a new scan line or frame.
If the analog video display is multicolor, then there would generally be one of the analog video signals 11 allocated to each color, such as for red, green, and blue. However, only one of the analog video signals, for instance, the one allocated to green, usually has the sync periods 16.
Recently, there has been a trend in the industry toward developing video displays which are driven by digital pixel data as opposed to analog video signals. An example of such a digital video display is the model LQ12D011 TFT LCD flat panel display manufactured and made commercially available by the Sharp Corporation, Japan. Thus, it has recently been desirable to convert the analog video signal 11 of FIG. 1 into digital pixel data for driving a digitally-controlled display. This process can be described graphically with reference to FIG. 1. Referring to FIG. 1, in the process of converting the analog video signal 11 into digital pixel data, the analog data 12 is converted to a series of digital codes, depending upon its amplitude at a given point in time. For Sharp's digital display device, the analog data 12, which typically represents 256 different intensity levels for a particular color, must be converted to only 8 intensity levels, as is represented in FIG. 1 by levels 0 through 7. The lowest possible color intensity level is commonly referred to as the "black" level, whereas the highest possible color intensity level is commonly referred to as the "white" level.
FIG. 2 illustrates a typical prior art input processing system 21 for converting the analog video signal 11 (FIG. 1) to a digital pixel data 22 on ADC output connection 23 is illustrated in FIG. 2. The input processing system 21 comprises the analog video signal 11 on a connection 18, which is transmitted to the input processing system 21 via a transmission line 24, commonly a coaxial cable or other like analog communications interface. A termination transistor R.sub.T, for instance, 75 ohms, is generally connected between the input connection 26 at the end of the transmission line 24 and ground so as to minimize ringing on the transmission line 24. A capacitor C1 receives the incoming analog video signal 11 and generally isolates the input processing system 21 from the signal 11 so that the analog video signal 11 can be shifted, or offset. Further, an analog-to-digital convertor (ADC) 28 receives the analog video signal 11 from the capacitor C1 on the ADC input 27 and converts it to a corresponding digital pixel data 22 on the ADC output connection 23. The ADC 28 converts the analog video signal 11 to a digital pixel data 26 under the control and timing of a dot (pixel) clock signal 29 produced by a dot clock generator 32. The dot clock generator 32 produces the dot clock signal 29 based upon the spacing of sync periods 16 within the analog video signal 11.
The peak-to-peak amplitude, i.e., the distance between the sync level 16 to the white level, of the analog video signal 11 can vary by approximately 10% in typical systems as a result of line impedance, temperature, and other inherent characteristics. Unfortunately, this predicament results in an inaccurate conversion of the analog data 12 into the discrete levels 0-7 for the ultimate digital pixel data. For example, as shown in FIG. 1, if the analog data 12 is shifted downwardly, the analog data 12 at level 7, for example, could be shifted down to level 6, thereby resulting in loss of the color corresponding to level 7. In order to compensate for this possible 10% variation, many prior art systems have attempted to clamp the analog video signal 11 to an analog voltage level. A prior art clamp circuit 25 for this purpose is shown in FIG. 2.
Referring to FIG. 2, the input processing system 21 attempts to shift, or offset, the signal amplitude of the incoming analog video signal 11 so that the voltage swing of the analog video signal 11 more closely matches the voltage range of the ADC, which is defined by ADC reference voltages V.sub.REF+, V.sub.REF-. This shifting process is typically performed with a clamp circuit 25, as shown in FIG. 2. The clamp circuit 25 is connected at the ADC input connection 26 of the ADC 28 and insures that the ADC input connection 26 does not drop below a certain predetermined voltage level.
The clamp circuit 25 generally comprises, as shown in FIG. 2, a diode D1 connected to a voltage divider having resistors R1, R2, which is powered by a supply voltage V.sub.S. When the voltage on the connection 27 drops below the predetermined voltage threshold, as defined by the diode D1, the diode D1 is turned on and current i.sub.0 flows through the diode D1 onto the connection 27, thereby increasing the voltage level of the connection 27. This action effectively shifts the voltage swing of the analog video signal 11 by establishing an offset (DC) voltage on the capacitor C1. In the alternative, when the voltage on the connection 27 is above the predetermined voltage threshold, as defined by the diode D1, the diode D1 is turned off and current i.sub.0 does not flow onto the connection 27. A clamp circuit similar to the foregoing input processing system 21 is set forth in Hans-Jurgen Desor ("Single Chip Video Processing System") IEEE Transactions on Consumer Electronics, August, 191, pages 182-189 and also in Graphics and Imaging Products, Applications Handbook, Brooktree Publications (1990).
However, the clamp circuits of the prior art, as are exemplified by the clamp circuit 25 in the input processing system 21 of FIG. 2, cause an offset voltage V.sub.T to appear across the termination transistor R.sub.T in the system 21 when the input processing system 21 injects current onto the ADC input connection 27 of the ADC 28. The offset voltage V.sub.T undesirably causes noise, spikes, and other distortion in the analog video signal 11, which adversely affects the operation of the input processing system 21 and ultimately the quality of the digital pixel data 22. Hence, a better approach is needed for shifting the incoming analog video signal 11 so that the aforementioned adverse effects are minimized.